View SM80952_4128070.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SyncMOS Technologies Inc.
May 2001
SM8051/80952
8 - Bit Micro-controller
with 4/8KB ROM embedded
Product List
SM8051L25, 25 MHz 4KB internal ROM MCU SM8052L25, 25 MHz 8KB internal ROM MCU SM8051C25, 25 MHz 4KB internal ROM MCU SM8052C25, 25 MHz 8KB internal ROM MCU SM8051C40, 40 MHz 4KB internal ROM MCU SM8052C40, 40 MHz 8KB internal ROM MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version 4.5V ~ 5.5V For C Version General 8051/8052 family compatible 12 clocks per machine cycle 4/8 KB internal ROM memory 128/256 bytes data RAM 2/3 16 bit timers/counters Four 8-bit I/O ports Full duplex serial channel Bit operation instruction Page free jumps 8-bit unsigned division 8-bit unsigned multiply BCD arithmetic Direct addressing Indirect addressing Nested interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and power down mode Code protection function One watch dog timer (WDT) Low EMI (inhibit ALE)
Description
The SM8051/8052 series product is an 8 - bit single chip micro controller with 4/8 KB ROM embedded. It provides hardware features and a powerful instruction set, necessary to make it a versatile and cost effective controller for those applications demand up to 32 I/O pins or need up to 4/8 KB ROM memory either for program or for data or mixed.
Ordering Information
yywwv SM8051/8052ihhk yy: year, ww:month v: version identifier { , A, B, ...} i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table}
Postfix P J Q
Package 40L PDIP 44L PLCC 44L QFP/TQFP
Pin/Pad Configuration page 2 page 2 page 2
Dimension page 13 page 14 page 15/16
Taiwan 4F, No. 1 Creation Road 1, Science-based Industrial Park, Hsinchu, Taiwan 30077 TEL: 886-3-579-2926 886-3-579-2988 FAX: 886-3-579-2960 886-3-578-0493
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/80952
Pin Configurations
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7 #EA
P1.1 P1.0 NC VDD P0.0/AD0 P0.1/AD1
P2.7/A15
P0.2/AD2
P0.3/AD3
P1.4
P1.3 P1.2
6
5
4
32
1 44 43 42 41 40
P1.5 P1.6 P1.7 RES RXD/P3.0 NC TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5
7 8 9 10 11 12 13
39 38 37
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA NC ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13
AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VDD NC P1.0 P1.1 P1.2 P1.3 P1.4
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
P2.6/A14 P2.5/A13
#PSEN
NC ALE
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 NC VSS XAL1 XAL2 P3.7/#RD P3.6/#WR
SM8051/8052 ihhJ 44L PLCC
(Top View)
36 35 34 33 32 31 30 29
SM8051/8052 inhQ 44L QFP (Top View)
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
#WR/P3.6
#RD/P3.7 XTAL2 XTAL1 VSS
A10/P2.2
A11/P2.3
A12/P2.4
A8/P2.0
A9/P2.1
NC
#INT0/P3.2
P1.5 P1.6 P1.7 RES RXD/P3.0
TXD/P3.1
#INT1/P3.3
T0/P3.4
NC
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RES RXD/P3.0 TXD/P3.1 #INT/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
8 9 10 11
12
13 14 15 16 17 18 19 20
Specifications subject to change without notice,contact your sales representatives for the most recent information.
2/16
Ver 1.1
SM8051/8052 07/2005
T1/P3.5
SM8051/8052ihhP 40L PDIP (Top View)
SyncMOS Technologies Inc.
May 2001 Block Diagram
Stack Pointer Decoder & Register 128/256 bytes RAM
SM8051/80952
Timer 2
Timer 1
Timer 0
WDT
RES Reset Circuit to pertinent blocks Acc to whole chip Buffer2 Buffer1
Buffer
DPTR
Vdd Vss Power Circuit
PC Incrementer
Interrupt Circuit
to pertinent blocks
ALU
Program Counter
PSW XTAL2 XTAL1 #EA ALE #PSEN to whole system Timing Generator
Register
Instruction Register
4/8 K bytes Port 0 Latch Port 1 Latch Port 2 Latch Port 3 Latch ROM Memory
Port 0 Driver & Mux 8
Port 1 Driver & Mux 8
Port 2 Port 3 Driver & Mux Driver & Mux 8 8
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 Pin Descriptions
40L PDIP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44L QFP Pin# 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 44L PLCC Pin# 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 Symbol Active P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RES RXD/P3.0 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 #PSEN ALE #EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o I/O Names
SM8051/80952
H
L/ L/ -
L/ L/ -
L L
bit 0 of port 1 bit 1 of port 1 bit 2 of port 1 bit 3 of port 1 bit 4 of port 1 bit 5 of port 1 bit 6 of port 1 bit 7 of port 1 Reset Receive data & bit 0 of port 3 Transmit data & bit 1 of port 3 low true interrupt 0 & bit 2 of port 3 low true interrupt 1 & bit 3 of port 3 Timer 0 & bit 4 of port 3 Timer 1 & bit 5 of port 3 external memory write & bit 6 of port 3 external memory read & bit 7 of port 3 Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of external memory address bit 1 of port 2 & bit 9 of external memory address bit 2 of port 2 & bit 10 of external memory address bit 3 of port 2 & bit 11 of external memory address bit 4 of port 2 & bit 12 of external memory address bit 5 of port 2 & bit 13 of external memory address bit 6 of port 2 & bit 14 of external memory address bit 7 of port 2 & bit 15 of external memory address program storage enable address latch enable external access bit 7 of port 0 & data/address bit 7 of external memory bit 6 of port 0 & data/address bit 6 of external memory bit 5 of port 0 & data/address bit 5 of external memory bit 4 of port 0 & data/address bit 4 of external memory bit 3 of port 0 & data/address bit 3 of external memory bit 2 of port 0 & data/address bit 2 of external memory bit 1 of port 0 & data/address bit 1 of external memory bit 0 of port 0 & data/address bit 0 of external memory Drive Voltage, +5 Vcc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
4/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/8052
SFR Memory MAP
$F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80
B ACC PSW T2CON IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 (Reserved) TH1 PCON SBUF WDTC RC2L RC2H TL2 TH2 SCONF
$FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8051/8052
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. The SM8051/8052 WDT has selectable divider input for the time base source clock. To select the divider input, the setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM8051/8052 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE Reset value 0 MSB WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS2 ~ PS0 : clock source divider bit PS [2:0] 000 001 010 011 100 101 110 111 Divider (OSC in) 8 16 32 64 128 256 512 1024 Time Period (ms) @40MHZ 13.1 26.21 52.42 104.8 209.71 419.43 838.86 1677.72 Unused * CLEAR 0 Unused * Unused * PS2 0 PS1 0
SM8051/8052
PS0 0 LSB
Watch Dog Timer Register - System Control Register (SCONF, $BF)
WDR Reset value 0
MSB
Unused *
Unused *
Unused *
Unused *
Unused *
Unused *
ALEI 0
LSB
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1 ALEI : ALE output inhibit bit, to reduce EMI The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8051/8052 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is no external program memory or no external data RAM in the system.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/80952
Operating Conditions
Symbol TA TS VCC5 VCC3 Fosc 25 Fosc 40 Description Operating temperature Storage temperature Supply voltage Supply voltage Oscillator Frequency Oscillator Frequency Min. 0 -55 4.5 3 3.0 3.0 Typ. 25 25 5.0 3.3 25 40 Max. 70 155 5.5 3.6 25 40 Unit.
o o
Remarks Ambient temperature under bias
C C V V
For C Version For L Version
MHz For 5V, 3.3V application MHz For 5V application
DC Characteristics
(12MHz, typical operating conditions, valid for SM8051/8052 series)
Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pulldown Resistance Pin Capacitance Power Supply Current
Valid
port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0 port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit
Test Conditions
2.4 90%Vcc 2.4 90%Vcc
50
V V V V V V V V V V uA -75 uA -650 + 10 uA 300 Kohm pF 10 mA 7 mA 4.5 10 uA
IOL=8mA (5V) / IOL=6mA (3.3V) IOL=6.5mA (5V) / IOL=6mA (3.3V) IOH=-800uA (only for VCC=5V) IOH=-80uA IOH=-60uA (only for VCC=5V) IOH=-10uA Vin=0.45V Vin=2.0V 0.45VSpecifications subject to change without notice,contact your sales representatives for the most recent information.
7/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 AC Characteristics
(25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT fosc=16MHz Min. Typ. Max 115 43 53 240 53 173 177 0 87 292 10 365 365 302 0 145 590 542 178 197 230 403 38 73 53
SM8051/80952
63 ICC VCC 8 Vcc
Variable fosc Unit Min. Typ. Max 2xT - 10 nS T - 20 nS T - 10 nS 4xT - 10 nS T - 10 nS 3xT - 15 nS 3xT - 10 nS 0 nS T + 25 nS 5xT - 20 nS 10 nS 6xT - 10 nS 6xT - 10 nS 5xT - 10 nS 0 nS 2xT + 20 nS 8xT - 10 nS 9xT - 20 nS 3xT - 10 3xT + 10 nS 4xT - 20 nS 7xT - 35 nS T - 25 nS T + 10 nS 5 nS 72 T -10 T + 10 nS nS nS nS nS 1/fosc nS ICC Idle mode test circuit
Remarks
ICC Active mode test circuit Vcc RST SM8051/8052 (NC) Clock Signal XTAL2 XTAL1 VSS PO EA
ICC VCC PO EA 8
Vcc
RST
SM8051/8052 (NC) Clock Signal XTAL2 XTAL1 VSS
Specifications subject to change without notice,contact your sales representatives for the most recent information.
8/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 Application Reference Valid for SM8051/8052
X'tal C1 C2 R X'tal C1 C2 R 3MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 9MHz 30 pF 30 pF open 33MHz 10 pF 10 pF 6.8K 12MHz 30 pF 30 pF open 40MHz 5 pF 5 pF 4.7K
R X2 C1 C2 XI X'tal
SM8051/80952
SM8051/8052
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
Data Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
1 2
ALE
#PSEN
#RD
5
7
3
PORT2
ADDRESS A15 - A8
3
4 Float
6 DATA in
8 Float ADDRESS or Float
PORT0
INST in Float
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
9/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 Program Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2
SM8051/80952
OSC ALE
1
2
#PSEN #RD,#WR
5
7
PORT2
3 ADDRESS A15 - A8 ADDRESS A15 - A8
PORT0
3 Float A7 - A0
4 Float
6 INST in
8 Float A7 - A0 Float INST in Float
Data Memory Write Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
1
ALE
#PSEN
#WR
5
6
2
PORT2
2
ADDRESS A15 - A8
3 DATA OUT
4 ADDRESS or Float
PORT0
INST
Float
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/80952
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1 inputs P0,P1
sampled
sampled
inputs P2,P3 Output by Mov Px,Src RxD at Serial Port Shift Clock (Mode 0)
current data next data
sampled
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V TCHCL TCLCX TCLCH TCHCX
Tm.I
#PSEN ALE PORT 0
External Program Memory Read Cycle
TPLPH
TLHLL TAVLL A0 - A7
TLLPL TLLAX TPLAZ TPLIV
TPXIZ TPXIX Instruction. IN A0 - A7
TAVIV
PORT 2
A8 - A15
A8 - A15
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 Tm.II External Data Memory Read Cycle
SM8051/80952
#PSEN
TYHLH
ALE
TLLDV TLLYL TRLRH
#RD
TAVLL
TLLAX TRLAZ A0 - A7 from Ri or DPL TAVYL TAVDV
TRLDV
TRHDZ TRHDX DATA IN A0 - A7 from PCL INSTRL IN
PORT 0
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Tm.III External Data Memory Write Cycle
#PSEN
TLHLL
TYHLH
ALE
TLLYL TWLWH
#WR
TAVLL TLLAX
TQVWX
TQVWH
TWHQX
PORT 0
A0-A7 from Ri or DPL
DATA OUT
A0-A7 From PCL
INSTRL IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/80952
40L 600mil PDIP Information
E S D E1
A1
A2 A
C
L e1 B1 B
eA a
Note: 1. Dimension D Max & include mold flash or tie bar burrs. 2. Dimension E1 does not include inter lead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dam bar protrusion/ infusion. 5. Controlling dimension is inch. 6. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 B B1 C D E E1 e1 L a eA S
Dimension in inch minimal/maximal - / 0.210 0.010 / 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0 / 15 0.630 / 0.670 - / 0.090
Dimension in mm minimal/maximal - / 5.33 0.25 / 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 0 / 15 16.00 / 17.02 - / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001 44L Plastic Chip Carrier (PLCC)
6 7 L
SM8051/80952
E
HE y
GE
D HD A2 A C A1
b1 e GD
b
Note: 1. Dimension D & E does not include inter lead flash. 2. Dimension b1 does not include dam bar protrusion/ intrusion. 3. Controlling dimension: Inch 4. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 b1 b C D E e GD GE HD HE L
y
Dimension in inch minimal/maximal - / 0.185 0.020 / 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 BSC 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 /
Dimension in mm minimal/maximal - / 4.70 0.51 / 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27 BSC 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 /
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/80952
44L Plastic Quad Flat Package
C L S e L1 2 R1 D2 D1 D b A2 3 R2 A1 Gage Plane 0.25 mm
E2 E1 E e1 A
seating plane e
C
Note: Dimension D1 and E1 do not include mold protrusion. Allowance protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined datum plane. Dimension b does not include dam bar protrusion. Allowance dam bar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dam bar cannot be located on the lower radius or the lead foot.
Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C
Dimension in Inch minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005 / 0.005 / 0.012 0.008 / 0 / 7 0 / 10 REF 7 REF 0.004
Dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73 / 1.03 1.60 0.13 / 0.13 / 0.30 0.20 / as left as left as left as left 0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
May 2001
SM8051/8052
44L Thin Plastic Quad Flat Package
Dimension in inch (REF) Symbol A A1 A2 b E1 E e t y L L1 minimal/maximal 0.047 (MAX) 0.004 +/- 0.002 0.039 +/- 0.002 0.012 (TYP) 0.472 +/- 0.004 0.394 +/- 0.004 0.031 (TYP) 0.005 (TYP) 0.003 (TYP) 0 ~ 7 0.024 +/- 0.006 0.039 (REF)
Dimension in mm (BASE) minimal/maximal 1.200 (MAX) 0.100 +/- 0.050 1.000 +/- 0.050 0.30 (TYP) 12.000 +/- 0.100 10.000 +/- 0.100 0.800 (TYP) 0.127 (TYP) 0.076 (TYP) 0 ~ 7 0.600 +/- 0.150 1.000 (REF)
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/16
Ver 1.1
SM8051/8052 07/2005

▲Up To Search▲

Price & Availability of SM80952

	To Download SM80952 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .